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GENLINX TMII GS9023A
Embedded Audio CODEC
DATA SHEET KEY FEATURES * single chip embedded audio solution * operates as an embedded audio multiplexer or demultiplexer * full support for 48kHz synchronous 20/24 bit audio * 4 channels of audio per GS9023A * cascadable architecture supports additional audio channels * multiplexes and demultiplexes arbitrary ANC data packets * support for 143, 177, 270, 360 and 540 Mb/s video standards * full processing of audio parity, channel status and user data * multiplexes and demultiplexes audio control packets * EDH generation and insertion when in Multiplex Mode * 3.3V core with 3.3V or 5V I/O (requires 5V supply) * complies with SMPTE 272M A, B, and C APPLICATIONS SDI Embedded Audio ORDERING INFORMATION
PART NUMBER GS9023ACFY PACKAGE 100 pin LQFP TEMPERATURE 0C to 70C
BRIEF DESCRIPTION The GS9023A is a highly integrated, single chip solution for the multiplexing/demultiplexing of digital audio channels into and out of digital video signals. The GS9023A supports the multiplexing/demultiplexing of 20 or 24-bit synchronous audio data with a 48kHz sample rate. Audio signals with different sample rates may be sample rate converted to 48kHz before and after the GS9023A using audio sample rate converters. Each GS9023A supports all the processing required to handle the multiplexing/demultiplexing of four digital audio channels. To simplify system design, the GS9023A seamlessly integrates with common AES/EBU digital audio receivers and transmitters. The cascadable architecture allows for the multiplexing/demultiplexing of additional audio channels with no external glue logic. The GS9023A supports video standards with rates from 143Mb/s to 540Mb/s. When in Multiplex Mode, the GS9023A supports the generation and insertion of EDH information according to SMPTE RP165. In combination with Gennum's GS9032, the GS9023A provides a low power, highly integrated two chip solution for SDI transmit applications. In combination with Gennum's GS7005, the GS9023A provides a low power, highly integrated two chip solution for SDI receive applications. The GS9023A requires a 3.3V power supply for internal core logic and a 3.3V or 5V power supply for device I/O.
GS9023A
Revision Date: May 2004 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com
Document No. 19795 - 6
WCINA/B AINA/B AUXEN
2 3 Convert Input Data Format Convert AES/EBU Format
MPX
S/P 10
MPX MPX 10 10 10 Audio Buffer
GS9023A
10
MPX
AM[2:0] SAFA/B CSA/B UDA/B VFLA/B MUTE ADDR[3:0] CS, WE, RE DATA[7:0] DIN[9:0] VM[2:0]
3 Convert Control Code
8
Add CRC 10 MPX Generate Audio Packets 8 Arbitrary Packet Buffer
Add EDH
10 DOUT[9:0]
7 8 10 3 Control Registers
9 b9=b8
10
Video Detection & Synchronization
Generate ANCI area 9 LOCK PKT[8:0] EDH_INS
MULTIPLEX MODE BLOCK DIAGRAM
TRS 10
ANCI DIN[9:0] 10 Video Detection & Synchronization
Delete ANCI 10
Delete TRS
DOUT[9:0]
Detect ANCI 10 Output Arbitrary Packet Output Control Code
3
LOCK BUFERR AUXEN PKT[8:0] SAFA/B CSA/B UDA/B VFLA/B WCOUT
9
8
Audio Buffer Control Registers
10
P/S
Add CRC
Convert Output Data Format Convert AES/EBU Format 3 AM[2:0]
2
AOUTA/B
7
8
ADDR[3:0], CS, WE, RE
DATA[7:0]
MUTE
DEMULTIPLEX MODE BLOCK DIAGRAM
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CONTENTS
1. PIN CONNECTIONS............................................................................................................................ 4 2. DETAILED DESCRIPTION ..................................................................................................................... 8 2.1 MULTIPLEX MODE ............................................................................................................... 8
GS9023A
2.1.1 VIDEO CLOCK INPUT............................................................................................................................................8 2.1.2 VIDEO DATA INPUT...............................................................................................................................................8 2.1.3 VIDEO DATA OUTPUT...........................................................................................................................................9 2.1.4 AUDIO CLOCK INPUT ...........................................................................................................................................9 2.1.5 AUDIO DATA INPUT ..............................................................................................................................................9 2.1.6 CONTROL CODE INPUT .......................................................................................................................................9 2.1.7 AUDIO DATA PACKETS ......................................................................................................................................11 2.1.8 EXTENDED AUDIO DATA PACKETS...................................................................................................................14 2.1.9 AUDIO CONTROL PACKETS...............................................................................................................................16 2.1.10 ARBITRARY DATA PACKETS ............................................................................................................................18 2.1.11 ERROR DETECTION ..........................................................................................................................................19
2.2 DEMULTIPLEX MODE ......................................................................................................... 19
2.2.1 VIDEO CLOCK INPUT..........................................................................................................................................19 2.2.2 VIDEO DATA INPUT.............................................................................................................................................19 2.2.3 VIDEO DATA OUTPUT.........................................................................................................................................20 2.2.4 AUDIO CLOCK INPUT .........................................................................................................................................21 2.2.5 AUDIO DATA OUTPUT ........................................................................................................................................21 2.2.6 CONTROL CODE OUTPUT..................................................................................................................................23 2.2.7 DETECTION OF AUDIO PACKETS ......................................................................................................................23 2.2.8 DETECTION OF EXTENDED AUDIO PACKETS ..................................................................................................24 2.2.9 DETECTION OF AUDIO CONTROL PACKETS....................................................................................................24 2.2.10 DETECTION AND OUTPUT OF ARBITRARY DATA PACKETS..........................................................................24 2.2.11 ERROR DETECTION ..........................................................................................................................................24
2.3 MULTIPLEX AND DEMULTIPLEX MODES ............................................................................... 25
2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 DELAY OF VIDEO AND AUDIO ...........................................................................................................................25 NON-STANDARD SAMPLE DISTRIBUTIONS ......................................................................................................25 HOST INTERFACE ...............................................................................................................................................25 RESET ..................................................................................................................................................................25 INTERCONNECTION WITH GS9032 OR GS7005 ...............................................................................................25 AUDIO CLOCK AND VIDEO CLOCK STABILITY IN MULTIPLEX MODE ............................................................25 INTERCONNECTION WITH GS9020 ...................................................................................................................25
3.
HOST INTERFACE TABLES ............................................................................................................... 26 3.1 MULTIPLEX MODE ............................................................................................................. 26 3.2 DEMULTIPLEX MODE ........................................................................................................ 29
4. PACKAGING INFORMATION .............................................................................................................. 37 5. REVISION HISTORY .......................................................................................................................... 37
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1.
PIN CONNECTIONS
TEST DATA2 DATA1 DATA0 GND BUFERR NC LOCK VDDIO DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 GND DOUT8 DOUT9 AOUTA AOUTB WC OUT NC VDDIO
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 GS9023A 38 88 37 89 (TOP VIEW) 36 90 35 91 34 92 33 93 32 94 31 95 30 96 29 97 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VDDIO DATA3 DATA4 DATA5 DATA6 DATA7 GND RE WE CS ADDR3 ADDR2 ADDR1 ADDR0 VDDINT ANCI TRS EDH_INS MUTE AM2 AM1 AM0 GND ACLK GND
GND PKTEN PKT0 PKT1 PKT2 PKT3 PKT4 PKT5 PKT6 PKT7 PKT8 VDDIO AUXEN CSB CSA UDB UDA VFLB VFLA SAFB SAFA GND TEST TEST VDDINT
GS9023A
VDDINT VM2 VM1 VM0 DEMUX/MUX DIN9 DIN8 DIN7 DIN6 DIN5 GND DIN4 DIN3 DIN2 DIN1 DIN0 VDDINT
NOTE: The GS9023A DOUT[9:0] MSB to LSB convention is compatible with the GS9022 but reversed with the GS9032 or GS7005. See Interconnection with GS9032 or GS7005 section.
PIN DESCRIPTIONS
NUMBER 1, 17, 26, 90 2-4 SYMBOL VDDINT VM[2:0] I TYPE DESCRIPTION +3.3V power supply pins for core logic. Video standard format. Used in conjunction with the TRS pin. VM[2] is the MSB and VM[0] is the LSB. See Table 1. Mode of operation. When set HIGH, the GS9023A operates in Demultiplex Mode. When set LOW, the GS9023A operates in Multiplex Mode. NOTE: A device reset must be performed when switching between Multiplex and Demultiplex Modes while the device is powered up. 6-10,12-16 DIN[9:0] I Parallel digital video signal input. DIN[9] is the MSB and DIN[0] is the LSB. The digital video input must contain TRS information. 11, 23, 25, 29, 50, 58, 71, 82, 98, 100 18 GND Device ground.
5
DEMUX/MUX
I
RESET
I
Device reset. Active low. NOTE: The video input to output data path will be interrupted during device reset.
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RESET WC INA WC INB AINA AINB GND PCLK GND
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PIN DESCRIPTIONS (CONTINUED)
NUMBER 19 SYMBOL WCINA TYPE I DESCRIPTION 48kHz word clock for channels 1 and 2. Used only when operating in Multiplex Mode and when the audio source is not an AES/EBU data stream. This pin should be grounded when inputting AES/EBU digital audio data or when operating in Demultiplex Mode. 48kHz word clock for channels 3 and 4. Used only when operating in Multiplex Mode and when the audio source is not an AES/EBU data stream. This pin should be grounded when inputting AES/EBU digital audio data or when operating in Demultiplex Mode. Audio signal input for channels 1 and 2. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Audio signal input for channels 3 and 4. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Video clock signal input. Connect to ground. Start of audio frame indicator for channels 1 and 2. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. SAFA is HIGH for audio frame 0 and LOW for all other audio frames. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023A. Start of audio frame indicator for channels 3 and 4. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. SAFB is set to HIGH for audio frame 0 and LOW for all other audio frames. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023A. Validity flag for channels 1 and 2. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. VFLA is HIGH when audio is invalid and LOW when audio is valid. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023A. Validity flag for channels 3 and 4. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. VFLB is HIGH when audio is invalid and LOW when audio is valid. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023A. User data for channels 1 and 2. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023A. User data for channels 3 and 4. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023A. Channel status for channels 1 and 2. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023A. Channel status for channels 3 and 4. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023A.
20
WCINB
I
GS9023A
21
AINA
I
22
AINB
I
24 27, 28, 75 30
PCLK TEST SAFA
I I/O
31
SAFB
I/O
32
VFLA
I/O
33
VFLB
I/O
34
UDA
I/O
35
UDB
I/O
36
CSA
I/O
37
CSB
I/O
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PIN DESCRIPTIONS (CONTINUED)
NUMBER 38 SYMBOL AUXEN TYPE I/O DESCRIPTION Extended audio enable. When HIGH, the GS9023A processes 24-bit audio samples. When LOW, the GS9023A processes 20-bit samples. In Multiplex Mode, this pin is an input and is supplied by the user. The setting is logical OR with the related A4ON setting in host interface register address 1h. In Demultiplex Mode, this pin is an output and is generated by the GS9023A.
GS9023A
39, 51, 67, 76
VDDIO
+3.3V or +5V power supply pins for device I/Os. In order for device I/O to be +5V tolerant VDDIO must be +5V. Device I/O are not +5V tolerant if VDDIO is +3.3V. I/O Arbitrary data I/O bus. In Multiplex Mode, the user must input the arbitrary data packet words starting from the secondary data identification (SDID) to the last user data word (UDW) according to SMPTE 291M. The GS9023A internally converts the data to 10 bits by generating the inversion bit (bit 9). The checksum (CS) word is also generated internally. In Demultiplex Mode, the GS9023A outputs the arbitrary data packet words starting from the SDID to the last UDW. PKT[8] is the MSB and PKT[0] is the LSB. See Figure 11 and Figure 16. Arbitrary data packet enable. In Multiplex Mode, PKTEN must be set HIGH one PCLK cycle before Arbitrary packet data is input to the device. In Demultiplex Mode, the output is set HIGH when outputting Arbitrary packet data. See Figure 11 and Figure 16. No Connect. Do not connect these pins. 48kHz word clock for channels 1, 2, 3 and 4. Valid only when operating in Demultiplex Mode. Audio signal output for channels 3 and 4. The AES/EBU digital audio output is biphase mark encoded. In all non-AES/EBU modes, the output is not bi-phase mark encoded. Audio signal output for channels 1 and 2. The AES/EBU digital audio output is biphase mark encoded. In all non-AES/EBU modes, the output is not bi-phase mark encoded. Parallel digital video signal output. DOUT[9] is the MSB and DOUT[0] is the LSB. Lock indicator. In Multiplex Mode, when HIGH, the video standard has been identified, the start of a new video frame has been detected and the device is multiplexing audio. NOTE: LOCK will not be set HIGH unless at least one of the audio channel enable bits is HIGH. See "CHACT" description in Table 14. In Demultiplex Mode, when HIGH, the video standard has been identified, the `lock' process selected by "ACTSEL" has been validated and the device is demultiplexing audio. See "ACTSEL" description in Table 15. NOTE: LOCK remains active regardless of the number of audio samples in the video stream after `lock' is achieved.
40-48
PKT[8:0]
49
PKTEN
I/O
52, 69 53
NC WCOUT
N/A O
54
AOUTB
O
55
AOUTA
O
56, 57, 59-66 68
DOUT[9:0] LOCK
O O
70
BUFERR
O
Buffer error. Indicates when an internal buffer overflow/underflow error has occurred. Valid only when the device is configured to operate in Demultiplex Mode. NOTE: If an internal buffer overflow/underflow condition occurs, the GS9023A does not mute the audio output.
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PIN DESCRIPTIONS (CONTINUED)
NUMBER 72-74, 77-81 83 84 85 86-89 91 SYMBOL DATA[0:7] RE WE CS ADDR[3:0] ANCI TYPE I/O I I I I I DESCRIPTION Host Interface data bus. DATA[7] is the MSB and DATA[0] is the LSB. Read enable for Host Interface. Active LOW. Write enable for Host Interface. Active LOW.
GS9023A
Chip select for Host Interface. Active LOW. Host Interface address bus. ADDR[3] is the MSB and ADDR[0] is the LSB. ANCI Selection. Valid in Demultiplex Mode only. When set HIGH, each ancillary data packet with a DID corresponding to either the audio packet DID, the extended audio packet DID or the arbitrary packet DID is removed from the video signal. The data contained in the packets are output at the corresponding pins. The various DIDs are user programmable in the internal registers and are accessible via the Host Interface. NOTE: When ancillary data packets are deleted, the GS9023A does not recalculate the EDH checkwords. When set LOW, all ancillary data packets remain in the video signal.
92
TRS
I
TRS Selection. Used in conjunction with the VM[2:0] pins to select video standard format. In Multiplex Mode, when the TRS pin is HIGH, TRS is added to a composite video signal. In Demultiplex Mode, when HIGH, TRS is removed from a composite video signal. See Table 1. EDH Insert Selection. Valid in Multiplex Mode only. When set HIGH, the GS9023A performs EDH functions according to SMPTE RP165. When set LOW, EDH is not inserted. This setting is logical OR with the related EDHON setting in host interface register address 1h. NOTE: Active picture and full field data words are updated from recalculated values but error flag information is replaced with the values programmed in the internal registers via the Host Interface.
93
EDH_INS
I
94
MUTE
I
Audio mute. In Multiplex Mode, when set HIGH, the embedded audio packets are forced to `0'. In Demultiplex Mode, when set HIGH, the output data is forced to "0". This setting is logical OR with the related MUTE setting in host interface address 4h. Audio mode format. In Multiplex Mode, AM[2:0] indicates the input audio data format. In Demultiplex Mode, AM[2:0] indicates the output audio data format. AM[2] is the MSB and AM[0] is the LSB. See Table 2. Input audio signal clock (128 fs). Synchronous to PCLK. In non-AES/EBU audio modes, the serial audio data is sampled on both edges of ACLK.
95-97
AM[2:0]
I
99
ACLK
I
NOTE: All unused inputs of the GS9023A should be connected to ground.
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2.
DETAILED DESCRIPTION When "VSEL" is LOW, the video input standard is selected by the VM[2:0] and TRS input pins. When "VSEL" is HIGH, the video input standard is selected by the "VMOD[2:0]" and "D2_TRS" bits in Host Interface Register #0h. The supported video input standards are listed in Table 1. After the user has specified the video input standard via the VM[2:0] and TRS pins or by setting Host Interface Register #0h, the GS9023A performs video standard detection to verify that the input video stream corresponds to the selected standard. The LOCK output pin and the "LOCK" bit of Host Interface Register #0h are then set HIGH if at least one of the audio channel enable bits "CHACT(4-1)" of Host Interface Register #1h is HIGH and the start of a video frame is detected. NOTE: The user must ensure that the video input format correctly corresponds to the video format being provided to the GS9023A. For 8-bit video operation, the "8BIT_SEL" bit of the Host Interface Register #2h must be set HIGH.
The GS9023A has two main modes of operation: Multiplex Mode and Demultiplex Mode. In Multiplex Mode, which is selected by setting the DEMUX/MUX input pin LOW, digital audio is embedded into a digital video stream. In Demultiplex Mode, which is selected by setting the DEMUX/ MUX input pin HIGH, digital audio is extracted from a digital video stream. Table 14 and Table 15 contain Host Interface Register descriptions for the Multiplex and Demultiplex Modes respectively.
2.1 MULTIPLEX MODE
GS9023A
2.1.1 Video Clock Input
A master video clock must be supplied to the PCLK pin corresponding to the selected video standard. The supported video input standards and corresponding clock frequencies are listed in Table 1.
2.1.2 Video Data Input
The video data DIN[9:0] is clocked into the GS9023A on the rising edge of PCLK. The video clock frequency must correspond to the video input standard selected. This is done via the "VSEL" bit of Host Interface Register #0h.
TABLE 1 VIDEO INPUT FORMATS SERIAL DIGITAL DATA RATE (MBPS) 143 143 270 360 540 177 177 270 360 540 540 PCLK FREQUENCY (MHZ) 14.3 14.3 27.0 36.0 54.0 17.7 17.7 27.0 36.0 54.0 54.0
VIDEO STANDARD 525/D2 (SMPTE259M) 525/D2 (SMPTE244M) 525/D1 Reserved 525/16:9 Reserved 525/4:4:4:4 (System #1) Reserved 625/D2 (with TRS) 625/D2 (without TRS) 625/D1 Reserved 625/16:9 Reserved 625/4:4:4:4 (System #2) 625/4:2:2P (System #4)
VM[2] OR "VMOD[2]" 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VM[1] OR "VMOD[1]" 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
VM[0] OR "VMOD[0]" 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
TRS OR "D2_TRS" 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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2.1.2.1 Synchronous Switch of Video Input
2.1.5 Audio Data Input
When a 525-line video input to the GS9023A undergoes a synchronous switch between two video sources, the two video sources may have 5-frame sequences which are not aligned. In this case, the GS9023A may not correctly detect the new 5-frame sequence, and the internal FIFO may overflow/underflow continuously. To avoid this problem, it is recommended that the user sets bits 5, 6, and 7 of Host Interface Register #2h HIGH (see bit descriptions in Table 14). Setting these bits HIGH will permit the device to reset the internal audio sample buffer when an overflow/ underflow condition is detected and mute the embedded audio packets during this reset.
2.1.3 Video Data Output
The serial audio data for channels 1 and 2 are input to the AINA pin. The serial audio data for channels 3 and 4 are input to the AINB pin. The GS9023A can multiplex 20 or 24 bit audio data samples. When the AUXEN pin or bit "A4ON" of Host Interface Register #1h is HIGH, the device processes 24 bit audio samples. When the AUXEN pin or "A4ON" register bit is LOW, the device processes 20 bit audio samples. On power up, the "A4ON" bit default is LOW. The GS9023A offers five predefined audio data input formats, selected via the AM[2:0] pins, which are listed in Table 2 and illustrated in Figure 1. The first four predefined formats relate to non-AES/EBU audio data while the fifth format corresponds to the AES/EBU audio format. The WCINA and WCINB pins should be grounded when inputting AES/EBU audio data as they are not used. The GS9023A supports muting of the audio data input. Multiplexed audio and extended data packets for all channels are forced to zero when the MUTE pin or "MUTE" bit of Host Interface Register #4h is set HIGH. When inputting AES/EBU data, the CRC byte and parity bit will be recalculated and inserted automatically.
2.1.6 Control Code Input
GS9023A
The video signal is output at the DOUT[9:0] pins. The video signal is synchronized to the rising edge of PCLK. When the GS9023A is properly configured, audio packets, extended audio packets, audio control packets and arbitrary data packets are multiplexed into the output video signal. When the video signal is a 525 line or 625 line D2 format, TRS information is added to the video signal if the TRS input pin or the "D2_TRS" and "VSEL" bits of Host Interface Register #0h are HIGH. EDH packets can also be inserted into the video signal by setting the EDH_INS pin HIGH or by setting the "EDHON" bit HIGH of Host Interface Register #1h. When selected, the GS9023A inserts EDH packets according to SMPTE RP165. NOTE: Active picture and full field data words are updated from recalculated values but error flag information is replaced with the values programmed in Host Interface Registers #Eh and #Fh. NOTE: In the 525/4:4:4:4 video standard, EDH packets should not be inserted as this can lead to TRS signal corruption. When EDH packets are not inserted, the "EDHDEL" bit of Host Interface Register #0h controls the deletion of EDH packets. When the "EDHDEL" bit is set LOW, EDH packets are deleted from the incoming video signal. When "EDHDEL" is set HIGH, EDH packets pass through the device unchanged. NOTE: "EDHDEL" functionality is valid only when the "CASCADE" bit of Host Interface Register #4h is LOW.
2.1.4 Audio Clock Input
When inputting non-AES/EBU audio data, the validity (V), user data (U) and channel status (C) bits of each audio data channel must be input to the corresponding pins (VFLA, VFLB; UDA, UDB; CSA, CSB). The signals must be updated on the rising edge of WCINA/B and remain constant for the entire word clock period (64 ACLK cycles). When inputting non-AES/EBU audio data, the SAFA and SAFB pins must be high for one frame out of 192 frames received to indicate the start of frame condition. When inputting AES/EBU audio data, the control code input pins should be grounded as they are not used.
TABLE 2 AUDIO INPUT FORMATS FORMATS AIN-MODE 0 AIN-MODE 1 AIN-MODE 2 AIN-MODE 3 AIN-AES/EBU Not Used Not Used Not Used WCINA/B User Supplied User Supplied User Supplied User Supplied Not Used AM[2] 0 0 0 0 1 1 1 1 AM[1] 0 0 1 1 0 0 1 1 AM[0] 0 1 0 1 0 1 0 1
A master audio clock (128 fs: 6.144MHz) must be supplied to the ACLK pin. This clock must be synchronized with the video signal input to the GS9023A. An audio word clock must also be supplied (fs: 48kHz) to the WCINA/B pins when using non-AES/EBU audio. The two 48kHz word clocks must also be synchronized to the video signal.
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GS9023A
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DATA
ACLK (128fs)
WCINA/B
SAFA/B
VFLA/B UDA/B CSA/B
LEFT CHANNEL LSB
0
MSB
RIGHT CHANNEL
LSB
0
AIN-MODE0
23
MSB 23
RIGHT CHANNEL LSB
23 8
LSB 0
MSB
LEFT CHANNEL
RIGHT CHANNEL
10 of 37
MSB
23 6
LSB 0
AIN-MODE1
7
0
MSB 23
8
RIGHT CHANNEL LSB
LEFT CHANNEL
RIGHT CHANNEL
AIN-MODE2
5
0
MSB 23
6
LSB
0 4
23 23
LEFT CHANNEL
MSB
AIN-MODE3
LSB 0
RIGHT CHANNEL
4
MSB 23 23
LSB
8
Audio sample word
LSB
27 28 29 30 31 0
AES/EBU Sub-frame format
MSB
AIN-AES/EBU
20bits 24bits Validity flag User data Channel status Parity bit
0
3
4
7
3
LSB 4
7
LSB 8
Audio sample word
MSB 27 28 29 30 31
Synchronization preamble
Z
Channel 1
Y
Channel 2
X
Channel 1
Y
Channel 2
X
Channel 1
Y
Channel 2
Sub-frame Frame 1 Frame 2
Sub-frame
Frame 0 (Start of Block)
Figure 1 Audio Input Format Timing Diagram
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2.1.7 Audio Data Packets
The GS9023A can multiplex up to four audio channels. The channels are selectable via the "CHACT(4-1)" bits of Host Interface Register #1h. The audio group (Audio packet data ID) for each device is configured in "AD20ID[3:0]" of Host Interface Register #3h. On power up, the four audio channels and audio group 1 are selected by default. By setting all the "CHACT(4-1)" bits in Host Interface Register #1h to zero, the GS9023A will be in bypass mode whereby any existing audio data packets, with the same audio group ID or otherwise, will pass through the device unchanged and no new audio data packets will be embedded. NOTE: Do not rely on default value. Reprogram on power up or reset.
The "CASCADE" bit in Host Interface Register #4h controls the manner in which multiplexing is performed. When "CASCADE" is LOW, the GS9023A deletes all existing ancillary packets. New packets are multiplexed at the first location after the end of active video (EAV) in the horizontal ancillary space (HANC). See Figure 2. When "CASCADE" is HIGH, the GS9023A multiplexes packets at the first free location in the horizontal ancillary (HANC) space after the end of active video (EAV) if there is sufficient space remaining to insert the packet. The GS9023A does not check if existing audio group samples are present in the video signal. Use caution in applications where the video signal contains existing audio packets to avoid adding identical group samples. See Figure 3. The GS9023A assumes that the ancillary space from the first free location is empty to the start of active video (SAV). Existing ancillary data packets (inserted by previous devices) in the video signal must be contiguous from the beginning of the HANC space or the insertion of a new audio data packet may overwrite existing data. See Figure 4.
GS9023A
Extended Audio Group 1
Extended Audio Group 2
Audio Group 1
Audio Group 2
EAV
Empty
Video Signal before GS9023A
Audio Group 1 (New)
EAV
Empty
Video Signal after GS9023A Insertion of Audio Group 1 ("CASCADE" = LOW)
Figure 2
Extended Audio Group 3
Extended Audio Group 4
Audio Group 3
Audio Group 4
EAV
Empty
Video Signal before GS9023A
Extended Audio Group 3 (Old)
Extended Audio Group 4 (Old)
Extended Audio Group 3 (New)
Audio Group 3 (Old)
Audio Group 4 (Old)
Audio Group 3 (New)
EAV
Empty
Video Signal after GS9023A Insertion of Audio Group 3 ("CASCADE" = HIGH)
Figure 3
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SAV
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Extended Audio Group 2
Audio Group 4
Audio Group 2
EAV
Empty
Empty
Video signal before GS9023A
SAV
GS9023A
Audio Group 2 (Corrupted) (Old)
Extended Audio Group 2 (Old)
Audio Group 4 (Old)
Audio Group 1 (New)
EAV
Empty
Video signal after GS9023A Insertion of Audio Group 1 ("CASCADE" = HIGH)
Figure 4
Audio Channels (CH1/2/3/4) VIDEO IN
S/P DIN AINA AINB PCLK ACLK DEMUX/MUX WCIN DOUT
Audio Channels (CH5/6/7/8)
Audio Channels (CH9/10/11/12)
Audio Channels (CH13/14/15/16) VIDEO OUT
DIN AINA AINB PCLK
DOUT
DIN AINA AINB
DOUT
DIN AINA AINB
DOUT
P/S
ACLK DEMUX/MUX WCIN
CLK 54MHz 36MHz 27MHz 17.7MHz 14.3MHz
PCLK ACLK DEMUX/MUX WCIN
PCLK ACLK DEMUX/MUX WCIN
PLL
CPU
Group DID No.
Figure 5 Multiplex Mode Cascadable Architecture
In cases where an audio data packet does not fit inside the remaining HANC space, the audio packet is discarded. In this case, the "ADERR" bit of Host Interface Register #7h is HIGH indicating an audio packet multiplexing error. The error bit is cleared once accessed by the Host Interface. By cascading four GS9023A devices, it is possible to multiplex up to 16 audio channels (according to SMPTE 272) in a component video signal as shown in Figure 5. NOTE 1: In the 525/D1 video format, only 15 channels of 24 bit audio can be multiplexed. NOTE 2: In cascade mode, audio samples embedded by the first GS9023A may be delayed by up to one audio sample with respect to the audio embedded by cascaded devices.
NOTE 3: When multiplexing audio data into a 525-line video signal at 29.97fps, the GS9023A establishes a 5-frame sequence based on the relationship between the incoming audio and the input video timing. When multiple GS9023As are used to multiplex several audio channels, the video signal will undergo a processing delay of 13 video clock cycles through each device. This may affect the timing relationship between the devices such that a different 5frame sequence may be established in a subsequent GS9023A. For example, Figure 6 shows two GS9023As cascaded to multiplex eight audio channels. The video signal will be delayed 13 video clock cycles in the first encoder. This timing discrepancy may cause the second GS9023A to establish a different 5-frame sequence from the first.
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VOUT[9-0] VIN[9-0] GS9023A (Multiplex Mode) AIN 1/2 AIN 3/4 GS9023A (Multiplex Mode)
GS9023A
(13 video clock delay) AIN 5/6 AIN 7/8
Figure 6 Multiplexing 2 Audio Groups using 2 GS9023As
X
X+1 X+2
X
X+1 X+2
X
X+1 X+2
X
X+1 X+2
X
X+1 X+2
X
X+1 X+2
AES 1, CH.1
AES 1, CH.1
AES 1, CH.1
AES 1, CH.2
AES 1, CH.2
AES 1, CH.2
AES 2, CH.1
AES 2, CH.1
AES 2, CH.1
AES 1, CH.2
AES 1, CH.2
AES 1, CH.2
AES 2, CH.1
AES 2, CH.1
AES 2, CH.1
AES 2, CH.2
AES 2, CH.2
AES 2, CH.2
ADF*
ADF*
ADF*
DBN
DID
DC
* The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M).
Figure 7 Audio Data Packet Structure with 4 Audio Channels, 1 Audio Group
Cascade operation is not recommended with a composite video signal, as there is insufficient HANC space for more than four channels of audio. Audio packet insertion is not guaranteed in this case. The audio data packet structure as described in SMPTE 272M is shown in Figure 7. The audio data packets words are defined as follows: ADF: Ancillary Data Flag. The ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the GS9023A. DID: Data ID. Audio data packets corresponding to an audio group are selected by programming "A20ID[3:0]" of Host Interface Register #3h for audio groups 1 to 4 as follows: Group 1: Fh (2FFh) Group 2: Dh (1FDh) Group 3: Bh (1FBh) Group 4: 9h (2F9h)
NOTE: The six most significant bits of the DID are internally generated by the GS9023A. DBN: Data Block Number. The data block number is used when data blocks within a common data ID are to be linked or to distinguish consecutive data blocks within a common data ID. The data block number continuously increments from 1 to 255 and is generated automatically by the GS9023A. DC: Data Count. The data count represents the number of user data words to follow (maximum of 255 words). The data count is automatically generated by the GS9023A. CS: Checksum. The checksum consists of nine bits. The checksum is used to determine the validity of the words data ID through user data. It is the sum of the nine least significant bits of the words data ID through user data. The checksum is automatically generated by the GS9023A. The serial audio data samples, are mapped into three contiguous ancillary data words (X, X+1, X+2) as shown in Table 3.
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CS
The audio packet data sample bits are defined as follows:
TABLE 3 AUDIO PACKET DATA SAMPLE STRUCTURE BIT b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 WORD X not b8 aud 5 aud 4 aud 3 aud 2 aud 1 aud 0 (LSB) ch 1 (MSB) ch 0 (LSB) Z WORD X+1 not b8 aud 14 aud 13 aud 12 aud 11 aud 10 aud 9 aud 8 aud 7 aud 6 WORD X+2 not b8 P C U V aud 19 (MSB) aud 18 aud 17 aud 16 aud 15
Z: The Z flag is set HIGH at the same sample coincident with the beginning of a new AES channel status block (frame 0) and is otherwise set LOW. In non-AES/EBU data input formats this bit is set to the value of the SAFA/B input pins at the rising edge of WCINA/B. ch[1:0]: Identification of the channels in an audio group as shown in Table 4. aud[19:0]: Twos complement linearly represented audio data. The audio data is input from the AINA and AINB pins. V: AES/EBU sample validity bit. If the audio sample is valid the bit is set LOW. If the audio sample is invalid, the bit is set HIGH. In non-AES/EBU data input formats, this bit is set to the value of the VFLA/B input pins at the rising edge of WCINA/B. U: AES/EBU user bit. In non-AES/EBU data input formats, this bit is set to the value of the UDA/B input pins at the rising edge of WCINA/B. C: AES/EBU audio channel status bit. In non-AES/EBU data input formats this bit is set to the value of the CSA/B input pins at the rising edge of WCINA/B. P: Even parity for the 26 previous bits in the audio data sample (excludes b9 in the first and second words). NOTE: The P bit is not the same as the AES/EBU parity bit. This bit is automatically generated by the GS9023A.
2.1.8 Extended Audio Data Packets
GS9023A
TABLE 4 CHANNEL IDENTIFICATION WITHIN THE AUDIO GROUPS CH 1 0 0 1 1 CH 0 0 1 0 1 GROUP 1 Channel 1 Channel 2 Channel 3 Channel 4 GROUP 2 Channel 5 Channel 6 Channel 7 Channel 8 GROUP 3 Channel 9 Channel 10 Channel 11 Channel 12 GROUP 4 Channel 13 Channel 14 Channel 15 Channel 16
The GS9023A can multiplex 20 or 24 bit audio samples. For 24 bit audio samples, the 20 MSBs of a 24 bit audio sample are contained in the audio data packets and the 4 LSBs are contained in an extended audio data packet as defined in SMPTE 272. The extended audio data packet is multiplexed immediately following the corresponding audio data packet. See Figure 8.
Audio Group 4
EAV
Empty
Video signal before GS9023A
Extended Audio Group 2 (New)
Audio Group 4 (Old)
Audio Group 2 (New)
EAV
Empty
Video signal after GS9023A Insertion of Audio Group 2 & Extended Audio Group 2 ("CASCADE" = HIGH)
Figure 8
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AES 1 CH.1/2
AES 2 CH.3/4
AES 1 CH.1/2
AES 2 CH.3/4
AES 1 CH.1/2
AES 2 CH.3/4
AES 1 CH.1/2
AES 2 CH.3/4
ADF*
ADF*
ADF*
DBN
DID
DC
* The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M).
CS
GS9023A
Figure 9 Extended Audio Data Packet Structure
To select 24 bit audio operation, the user must set the AUXEN pin or the "A4ON" bit of Host Interface Register #1h HIGH. When the AUXEN pin or "A4ON" bit is HIGH, the GS9023A does not multiplex the audio data packet and the associated extended audio data packet if there is insufficient room for both in the HANC space. In this case, the "ADERR" bit of Host Interface Register #7h is set HIGH, indicating an audio packet multiplexing error. The error bit is cleared when accessed by the Host Interface. The audio group (Extended packet data ID) for each device is configured in "AD4ID[3:0]" of Host Interface Register #3h. On power up, audio group 1 is selected by default. By cascading four GS9023A devices, it is possible to multiplex up to 16 audio channels (according to SMPTE 272) in a component video signal as shown in Figure 5. NOTE: In the 525/D1 video format, only 15 channels of 24 bit audio can be multiplexed in the cascade configuration. The extended audio data packet structure as described in SMPTE 272M is shown in Figure 9. The extended audio data packets words are defined as follows: ADF: Ancillary Data Flag. The ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the GS9023A. DID: Data ID. Extended audio data packets corresponding to an audio group are selected by programming "A4ID[3:0]" of Host Interface Register #3h for audio groups 1 to 4 as follows: Group 1: Eh (1FEh) Group 2: Ch (2FCh) Group 3: Ah (2FAh) Group 4: 8h (1F8h) NOTE: The six most significant bits of the DID are automatically generated by the GS9023A.
DBN: Data Block Number. The data block number is used when data blocks within a common data ID are to be linked or to distinguish consecutive data blocks within a common data ID. The data block number continuously increments from 1 to 255 and is generated automatically by the GS9023A. DC: Data Count. The data count represents the number of user data words to follow (maximum of 255 words). The data count is automatically generated by the GS9023A. DATA WORDS: The extended audio data samples are mapped into ancillary data words as shown in Table 5.
TABLE 5 EXTENDED AUDIO PACKET DATA SAMPLE STRUCTURE BIT b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ANC DATA WORD not b8 a y3 (MSB) y2 y1 y0 (LSB) x3 (MSB) x2 x1 x0 (LSB)
The extended audio packet data sample bits are defined as follows: x[3:0]: Auxiliary data from subframe 1. y[3:0]: Auxiliary data from subframe 2. a: Address pointer. LOW for channels 1 and 2, and HIGH for channels 3 and 4. This bit is internally generated by the GS9023A. CS: Checksum. The checksum consists of nine bits. The checksum is used to determine the validity of the words data ID through user data. It is the sum of the nine least significant bits of the words data ID through user data. The checksum is automatically generated by the GS9023A.
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2.1.9 Audio Control Packets
The audio control packet structure is detailed in SMPTE 272M. The audio group (Audio control packet data ID) for each device is configured in "ACID[3:0]" of Host Interface Register #4h. The Audio control parameters are configured in Host Interface Registers #Ah, #Bh, #Ch and #Dh. The audio control packet multiplexing positions for the various video standards are listed in Table 6. In a component video signal, a maximum of 4 audio control packets can be multiplexed in a cascade connection. On power up, audio group 1 is selected by default. The GS9023A determines if multiplexing is possible by searching for the first free location in the HANC space after the signal EAV and calculates if there is sufficient remaining space to insert the audio packet. Existing ancillary data packets (inserted by previous devices) in the video signal must be contiguous from the beginning of the HANC space or the insertion of a new audio data packet may overwrite existing data. In cases where an audio control data packet does not fit inside the remaining HANC space, the audio
control packet is discarded. In this case, the "ACERR" bit of Host Interface Register #7h is HIGH indicating an audio control packet multiplexing error. The error bit is cleared when accessed by the Host Interface. The audio control packet structure as described in SMPTE 272M is shown in Figure 10.
TABLE 6 MULTIPLEXING POSITIONS FOR AUDIO CONTROL PACKETS VIDEO STANDARD 525/D2 525/D1 525/16:9 525/4:4:4:4 625/D2 625/D1 625/16:9 625/4:4:4:4 625/4:2:2P MULTIPLEXING LINES 12/275 12/275 12/275 12/275 8/321 8/321 8/321 8/321 15/641 HORIZONTAL STARTING POSITION 795 1444 1924 2884 972 1444 2277 2884 1444 HORIZONTAL ENDING POSITION 849 1711 2283 3427 1035 1723 2299 3451 1723
GS9023A
DELC0
DELC1
DELC2
DELD0
DELD1
DELD2
DELA0
DELA1
DELA2
DELB0
DELB1
DELB2
AF1-2
AF3-4
ADF*
ADF*
ADF*
RSRV
RSRV
DBN
RATE
ACT
DID
DC
* The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M).
Figure 10 Audio Control Packet Structure
The audio control packets words are defined as follows: ADF: Ancillary Data Flag. The ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the GS9023A. DID: Data ID. Audio control packets corresponding to an audio group are selected by programming "ACID[3:0]" of Host Interface Register #4h for audio groups 1 to 4 as follows: Group 1: Fh (1EFh) Group 2: Eh (2EEh) Group 3: Dh (2EDh) Group 4: Ch (1ECh) NOTE: The six most significant bits of the DID are automatically generated by the GS9023A.
DBN: Data Block Number. The data block number is used when data blocks within a common data ID are to be linked or to distinguish consecutive data blocks within a common data ID. The data block number continuously increments from 1 to 255 and is generated automatically by the GS9023A. DC: Data Count. The data count represents the number of data words to follow. The data count has a fixed value of 212h and is automatically generated by the GS9023A. AF1-2: Audio frame number for channels 1 and 2. AF3-4: Audio frame number for channels 3 and 4. For an audio sampling frequency of 48kHz, the audio frame numbers are sequenced from one to five for 525 line video standards and fixed at one for 625 line video standards. The audio frame numbers, AF1-2 and AF3-4, are automatically generated by the GS9023A and set to the same value. The sequence count is started at one at the first frame after `lock' is achieved.
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RATE: Sampling frequency. The GS9023A operates at a fixed sampling frequency of 48kHz. The audio control packet RATE word structure is shown in Table 7.
TABLE 7 AUDIO CONTROL PACKET RATE WORD STRUCTURE BIT b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RATE WORD not b8 not used (fixed to 0) y2 (MSB, fixed to 0) y1 (fixed to 0) y0 (LSB, fixed to 0) bsync x2 (MSB, fixed to 0) x1 (fixed to 0) x0 (LSB, fixed to 0) async
a(4-1): Individual active channel status indicator. The bits correspond directly to the "CHACT(4-1)" bits of Host Interface Register #1h. The bits are set HIGH for each active channel in a given audio group. The correlation of the active channels for the four active audio groups is shown in Table 9.
TABLE 9 AUDIO CONTROL PACKET ACTIVE CHANNEL CONFIGURATION GROUP1 CHACT 1 CHACT 2 CHACT 3 CHACT 4 Channel 1 Channel 2 Channel 3 Channel 4 GROUP2 Channel 5 Channel 6 Channel 7 Channel 8 GROUP3 Channel 9 Channel 10 Channel 11 Channel 12 GROUP4 Channel 13 Channel 14 Channel 15 Channel 16
GS9023A
The audio control packet RATE word bits are defined as follows: x[2:0], y[2:0]: Audio sampling rate for subframe 1 and 2 respectively. Fixed at 48kHz. async, bsync: Set LOW when each audio channel pair is operating synchronously and set HIGH when operating asynchronously. Forced LOW due to synchronous operation. ACT: The ACT word indicates the active group channels. The audio control packet ACT word structure is shown in Table 8.
TABLE 8 AUDIO CONTROL PACKET ACT WORD STRUCTURE BIT b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ACT WORD not b8 p reserved (set to 0) reserved (set to 0) reserved (set to 0) reserved (set to 0) a4 a3 a2 a1
DELx(0-2): Indicates the amount of accumulated audio processing delay relative to video, measured in audio sample intervals for each of the channels. Positive values indicate that the video leads the audio. The audio control packets delay word structure is shown in Table 10.
TABLE 10 AUDIO CONTROL PACKET DELAY STRUCTURE BIT b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DELX0 not b8 dela/b 7 dela/b 6 dela/b 5 dela/b 4 dela/b 3 dela/b 2 dela/b 1 dela/b 0 (LSB) e DELX1 not b8 dela/b 16 dela/b 15 dela/b 14 dela/b 13 dela/b 12 dela/b 11 dela/b 10 dela/b 9 dela/b 8 DELX2 not b8 dela/b 25 (Sign) dela/b 24 (MSB) dela/b 23 dela/b 22 dela/b 21 dela/b 20 dela/b 19 dela/b 18 dela/b 17
The audio control packet delay word bits are defined as follows: e: Indicates valid audio delay data when set HIGH. Corresponds to the "ACDLY" bit of Host Interface Register #Dh. dela/b[25:0]: The audio channel pair delay is programmed in bits "DELA/B[25:0]" of Host Interface Register #Ah, #Bh, #Ch and #Dh. DELA[25:0] corresponds to the delay for channels 1 and 2. "DELB[25:0]" corresponds to the delay for channels 3 and 4. RSRV: Reserved. The word is fixed at 200h and is automatically generated by the GS9023A. CS: Checksum. The checksum consists of nine bits. The checksum is used to determine the validity of the words data ID through user data. It is the sum of the nine least significant bits of the words data ID through user data. The checksum is automatically generated by the GS9023A.
The audio control packet ACT word bits are defined as follows: p: Even parity for bits b0 to b7.
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2.1.10 Arbitrary Data Packets
The GS9023A is capable of multiplexing arbitrary data packets according to SMPTE 291M. Typically, this consists of linear time code data (LTC), vertical interval time code data (VITC) or other data which is multiplexed once per field. The user must input the 9 LSBs starting from the secondary data identification (SDID) word to the last user data word (UDW) of the ancillary data packet containing arbitrary data. The CS word and bit 10 of all words in the packet are internally generated. The arbitrary data packet data ID is configured in "PKTID[7:0]" of Host Interface Register #5h. To process arbitrary data, the user must set the "PKON" bit of Host Interface Register #1h. Also, the user must specify the line number in "PKTLINE[7:0]" in Host Interface Register #9h. This value corresponds to the line in video field 1 in which the user wants the arbitrary data packet to be multiplexed. The corresponding line in field 2 is automatically selected for arbitrary data packet multiplexing. Arbitrary data is typically multiplexed during the active portion of the line in the vertical blanking interval (VBI). Care should be taken to avoid selecting a line in the active picture. Table 11 lists recommended multiplexing lines according to the video standard.
TABLE 11 MULTIPLEX POSITION FOR ARBITRARY DATA PACKET VIDEO STANDARD 525/D2 525/D1 525/16:9 RECOMMENDED MULTIPLEX LINE 9/272 14/277 14/277
NOTE: In field #1, the line number is offset by one from the value configured in "PKTLINE[7:0]".Arbitrary data is input to the GS9023A as shown in Figure 11. The data is stored in an internal arbitrary data packet buffer which is cleared at the end of every field. Arbitrary data must be written to the buffer before the line number specified in "PKTLINE[7:0]" is reached in order for the packet to be multiplexed. Data is input to the PKT[8:0] pins and clocked in on the rising edge of PCLK. PKTEN must be set HIGH one PCLK cycle before the data at the PKT[8:0] inputs is valid. PKTEN must go LOW one PCLK cycle before the last user data word (UDW) is input to the PKT[8:0] inputs. Parity (bit 8) for each UDW can be enabled by setting the "PKTPRTY" bit of Host Interface Register #8h to HIGH. When "PKTPRTY" is HIGH, data input at PKT[8] is overwritten by the parity bit. Up to 255 words (253 UDWs + SDID + DC) can be input and multiplexed once per field. The arbitrary data packet structure as described in SMPTE 291M is shown in Figure 11.
GS9023A
HORIZONTAL STARTING POSITION (WORD #) 340 0 0
HORIZONTAL ENDING POSITION (WORD #) 360 1439 1919
NOTE: 525/4:4:4:4 and all 625 line video standards are not supported. * Horizontal Starting Position 0 is the first word of the active picture.
1 clk
1 clk
PCLK (I) PKTEN (I) PKT[8:0] (I) Valid data
ADF 1,2
ADF 1,2
ADF 1,2
DID 2
SDID
UDW
UDW
UDW
UDW
UDW
UDW
NOTE: 1 - The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M). 2 - The ADF, DID and CHKSUM words are automatically generated by the GS9023A.
Figure 11 Arbitrary Data Packet Input Timing Diagram
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DC
The arbitrary data packet words are defined as follows: ADF: Ancillary Data Flag. The ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the GS9023A. DID: Data ID. Configured in "PKTID[7:0]" of Host Interface Register #5h. The two most significant bits are internally generated by the GS9023A. SDID: Secondary Data ID. The Secondary Data ID is handled as user input data. DC: Data Count. The data count represents the number of user data words to follow, up to a maximum of 255 words. The data count is handled as user input data. For the GS9023A the maximum data count is 253 since the total number of words that can be input is 255 less the SDID and DC words. UDW: User Data Word. CS: Checksum. The checksum consists of nine bits. The checksum is used to determine the validity of the words data ID through user data. It is the sum of the nine least significant bits of the words data ID through user data. The checksum is automatically generated by the GS9023A.
2.1.11 Error Detection
2.2
DEMULTIPLEX MODE
2.2.1 Video Clock Input
A master video clock must be supplied to the PCLK pin corresponding to the selected video signal. The supported video input standards and corresponding clock frequencies are listed in Table 1.
GS9023A
2.2.2 Video Data Input
The video data DIN[9:0] is clocked in to the GS9023A on the rising edge of PCLK. The video clock frequency must correspond to the video input standard selected. This can be done with the VM[2:0] and TRS input pins or selected via the "VSEL" bit of Host Interface Register #0h. When "VSEL" is set HIGH, the video input standard is selected by "VMOD[2:0]" and "D2_TRS" in Host Interface Register #0h. The supported video input standards are listed in Table 1. After the user has specified the video input standard via the VM[2:0] and TRS pins or in Host Interface Register #0h, the GS9023A performs video standard detection to verify that the input video stream corresponds to the selected standard. The GS9023A then performs a `lock' procedure, as selected by the "ACTSEL" bit of Host Interface Register #4h, to determine if the audio is synchronous to the video. When "ACTSEL" is LOW, the GS9023A counts the number of audio samples present in a frame or multiple frames, depending on the video standard selected. `Lock' is achieved if the required number of samples are detected for 48kHz synchronous audio. When "ACTSEL" is HIGH, the GS9023A `locks' by detecting the presence of an audio control packet corresponding to the DID configured in "ACID[3:0]" of Host Interface Register #4h and occurring at the expected line and position as listed in Table 6. If the video signal does not contain audio control packets, `lock' will not occur. Once `lock' is achieved the LOCK output pin and the "LOCK" bit of Host Interface Register #0h are set HIGH and audio demultiplexing begins. The LOCK output pin and the "LOCK" bit stay active regardless of the number of samples in the video stream after `lock' is achieved. The GS9023A drops out of `lock' when there are no more packets detected in the video stream.
The GS9023A provides error status information in Host Interface Register #7h as described in Table 14. All errors are cleared when Host Interface Register #7h is read.
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2.2.3 Video Data Output
The video signal is output at the DOUT[9:0] pins. The video signal is synchronized to the rising edge of PCLK. The GS9023A is capable of removing audio, extended audio, arbitrary and audio control packets from the video stream. To remove packets, the user must set the ANCI pin HIGH or set the "VSEL" and "ADEL" bits of Host Interface Register #0h HIGH. The GS9023A then removes each packet having a DID corresponding to either the audio DID, the extended audio DID or the arbitrary data DID stored in the Host Interface Registers from the video stream. See Figure 12.
NOTE: The GS9023A passes EDH packets through unchanged in the Demultiplex Mode. If any audio, extended audio, arbitrary or audio control packets are deleted by the GS9023A, the EDH CRC words become invalid. When the ANCI pin or "ADEL" bit is LOW, all ancillary data packets remain in the video signal. See Figure 13. TRS can also be removed from a 525/625 D2 video signal when the TRS pin is set HIGH or the "VSEL" and "D2_TRS" bits of Host Interface Register #0h are set HIGH.
GS9023A
Extended Audio Group 1
Extended Audio Group 2
Audio Group 1
Audio Group 2
EAV
Empty
Video signal before GS9023A
Extended Audio Group 2 (Old)
Audio Group 2 (Old)
EAV
Empty
Empty
Video signal after GS9023A Removal of Audio Group 1 & Extended Audio Group 1 (ANCI = HIGH or "VSEL" and "ADEL" = HIGH)
Figure 12
Extended Audio Group 1
Extended Audio Group 2
Audio Group 1
Audio Group 2
EAV
Empty
Video signal before GS9023A
Extended Audio Group 1 (Old)
Extended Audio Group 2 (Old)
Audio Group 1 (Old)
Audio Group 2 (Old)
EAV
Empty
Video signal after GS9023A Removal of Audio Group 1 & Extended Audio Group 1 (ANCI = LOW or "VSEL" = HIGH and "ADEL" = LOW)
Figure 13
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2.2.4 Audio Clock Input
The user must input a master audio clock (128 fs: 6.144MHz) at the ACLK clock terminal. This clock must be synchronized with the video signal input to the GS9023A. The audio word clock inputs WCINA and WCINB must be grounded. NOTE: The long term jitter present on the ACLK must be less than half the audio clock period.
2.2.5 Audio Data Output
The GS9023A offers five predefined audio data output formats, selected via the AM[2:0] pins, which are listed in Table 12 and illustrated in Figure 14. The first four predefined formats relate to non-AES/EBU audio data while the fifth format corresponds to the AES/EBU audio format. During reset, the audio outputs are forced LOW. The GS9023A supports muting of the audio data outputs. The output serial audio samples are forced to zero when the MUTE pin or "MUTE" bit of Host Interface Register #4h are set HIGH. The audio data outputs are also muted when there is no video input signal.
TABLE 12 AUDIO OUTPUT FORMATS FORMATS AOUT-MODE 0 AOUT-MODE 1 AOUT-MODE 2 AOUT-MODE 3 AOUT-AES/EBU Not Used Not Used Not Used WCOUT Active 48kHz Active 48kHz Active 48kHz Active 48kHz AM[2] 0 0 0 0 1 1 1 1 AM[1] 0 0 1 1 0 0 1 1 AM[0] 0 1 0 1 0 1 0 1
GS9023A
The serial audio data for channels 1 and 2 are output at the AOUTA pin. The serial audio data for channels 3 and 4 are output at the AOUTB pin. Both outputs are synchronized to the rising edge of ACLK. The GS9023A can demultiplex 20 or 24 bit audio data samples. When 24 bit audio samples are detected, the AUXEN pin and bit "A4ON" of Host Interface Register #1h are set HIGH. When 20 bit audio samples are detected the AUXEN pin and "A4ON" register bit are set LOW. When AUXEN and "A4ON" are LOW, bits 4-7 of the AES/EBU output data format are set to "0". In the non-AES/EBU formats, bits 0-3 are set to "0". See Figure 14.
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GS9023A
GENNUM CORPORATION
DATA
ACLK (128fs)
WCOUT
SAFA/B
VFLA/B UDA/B CSA/B
LEFT CHANNEL LSB
0
MSB
RIGHT CHANNEL
LSB
0
AOUT-MODE0
23
MSB 23
RIGHT CHANNEL LSB
0 23 8
LSB 0
MSB
LEFT CHANNEL
RIGHT CHANNEL
AOUT-MODE1
7
MSB 23
8
RIGHT CHANNEL LSB
23 6
LSB 0
MSB LEFT CHANNEL
RIGHT CHANNEL
22 of 37
LSB
0 4
23 23
AOUT-MODE2
5
0
MSB 23
6
LEFT CHANNEL
MSB
AOUT-MODE3
LSB 0
RIGHT CHANNEL
4
MSB 23 23
LSB
7 8
Audio sample word
LSB
27 28 29 30 31 0
AES/EBU Sub-frame format
MSB
AOUT-AES/EBU
20bits 24bits Validity flag User data Channel status Parity bit
0
3
4
3
LSB 4
7
LSB 8
Audio sample word
MSB 27 28 29 30 31
Synchronization preamble
Z M X Channel 1 Y Channel 2 X Channel 1 Y Channel 2
Channel 1
Y
Channel 2
Sub-frame Frame 1 Frame 2
Sub-frame
Frame 0 (Start of Block)
Figure 14 Audio Data Output Formats
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2.2.6 Control Code Output
In the non-AES/EBU output formats, the V, U and C bits are output separately from the audio data stream. The bits are output respectively to the VFLA/B, UDA/B and CSA/B pins according to the channel pair to which they belong and change state on the rising edge of WCOUT. The SAFA/B output pins are set to HIGH for one audio frame out of 192 frames to mark the start of a block. In the AES/EBU audio output format, the respective pins are not used.
2.2.7 Detection of Audio Packets
NOTE: When multiple audio groups are embedded in the video stream, the status bits "CHACT(4-1)" are only valid if the audio group being extracted immediately follows the EAV. If the audio group does not immediately follow the EAV, the device will still de-embed the audio correctly, however, the "CHACT(4-1)" bits will be invalid. If no corresponding audio packets are found on the active video line, the "CHACT(4-1)" bits are set LOW. By connecting four GS9023A devices in parallel, it is possible to demultiplex up to 16 audio channels in a component video signal as shown in Figure 15. On power up, audio group 1 is selected by default. NOTE: When more than two channels of audio are embedded in an incoming audio data packet, audio samples from channel 1 must be embedded in either the 1st or 2nd sample position after the start of the audio data packet. Please refer to SMPTE 272M for details of the audio data packet formatting.
GS9023A
The GS9023A can demultiplex up to four audio channels of an audio group. The audio group (Audio packet data ID) for each device is configured in "AD20ID[3:0]" of Host Interface Register #3h. When the corresponding audio packets are found on the active video line, the GS9023A sets the respective "CHACT(4-1)" bits of Host Interface Register #1h.
VIDEO INPUT WITH 16 CH. AUDIO DATA S/P CLK 54MHz 36MHz 27MHz 17.7MHz 14.3MHz 10 DIN DOUT 10 AUDIO OUTPUT CH. 1/2 AUDIO OUTPUT CH. 3/4 WORD CLOCK #1 WORD CLOCK #1
PLL
128fs(6.144MHz) Group DID No.
AOUTA AOUTB PCLK WCOUT VDD ACLK DEMUX/MUX GS9023A #1
CPU 10 DIN DOUT 10 AUDIO OUTPUT CH. 5/6 AUDIO OUTPUT CH. 7/8 WORD CLOCK #2 WORD CLOCK #2
AOUTA AOUTB PCLK WCOUT VDD ACLK DEMUX/MUX GS9023A #2 10 DIN DOUT 10
AOUTA AOUTB PCLK WCOUT VDD ACLK DEMUX/MUX GS9023A #3 10 DIN DOUT 10
AUDIO OUTPUT CH. 9/10 AUDIO OUTPUT CH. 11/12 WORD CLOCK #3
WORD CLOCK #3
AOUTA AOUTB PCLK WCOUT VDD ACLK DEMUX/MUX GS9023A #4
AUDIO OUTPUT CH. 13/14 AUDIO OUTPUT CH. 15/16 WORD CLOCK #4
WORD CLOCK #4
Time
Figure 15 Demultiplex Mode Parallel Architecture
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2.2.8 Detection of Extended Audio Packets
2.2.10 Detection and Output of Arbitrary Data Packets
The GS9023A can demultiplex 20 or 24 bit audio samples. For 24 bit audio samples, the 20 MSBs of a 24 bit audio sample are contained in the audio data packets and the 4 LSBs are contained in an extended audio data packet as defined in SMPTE 272. The audio group (Extended packet data ID) for each device is configured in "AD4ID[3:0]" of Host Interface Register #3h. When the corresponding extended audio packets are detected on the active video stream, the GS9023A sets the AUXEN pin and the "A4ON" bit of Host Interface Register #1h to HIGH. If no corresponding extended audio packets are found on the active video line, the AUXEN pin and "A4ON" bit are set to LOW. On power up, audio group 1 extended audio packets are selected by default.
2.2.9 Detection of Audio Control Packets
The GS9023A is capable of demultiplexing arbitrary data packets according to SMPTE 291M. There are no limitations on the number of packets that can be demultiplexed and the packets can be located outside of the vertical blanking interval (VBI). The arbitrary data packet data ID is configured in PKTID[7:0] of Host Interface Register #5h. When the configured ID is detected in the active video or HANC area, data on the PKT[8:0] pins is clocked out on the rising edge of PCLK. The GS9023A sets the PKTEN output pin HIGH, when the data at the PKT[8:0] outputs is valid. PKTEN is set LOW when the last user data word (UDW) is output from PKT[8:0]. Figure 16 shows the output timing.
2.2.11 Error Detection
GS9023A
The audio group (Audio control packet data ID) for each device is configured in "ACID[3:0]" of Host Interface Register #4h. When the configured ID is detected on the designated video lines (see Table 6), the "ACON" bit of Host Interface Register #1h is set. The corresponding Audio control parameters are stored in Host Interface Registers #Ah, #Bh, #Ch and #Dh. If an audio control packet is not detected or found in non-designated video lines, "ACON" is set to LOW. However, the information in the audio control packets found in non-designated lines is considered valid and is stored in Host Interface Registers #Ah, #Bh, #Ch and #Dh. On power up, audio group 1 audio control packets are selected by default.
1 clk
The GS9023A provides error status information in Host Interface Registers #7h, #8h and #9h as described in Table 15. Register #7 contains error information on audio sampling and CRC conditions. Register #8 contains error information on audio packet data block number and data count. Register #9 contains error information on Control packets. Errors are cleared when the respective Host Interface Register is read.
PCLK (I) PKTEN (O) PKT[8:0] (O) Valid data
X+(N-2)
X+(N-1)
NOTE: 1 - The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M).
Figure 16 Arbitrary Data Output Timing Diagram
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CHKSUM
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ADF 1
ADF 1
ADF 1
SDID
DID DID
X+N
X+1
X+2
X+3
DC
X
2.3
MULTIPLEX AND DEMULTIPLEX MODES
2.3.4 Reset
2.3.1 Delay of Video and Audio
The GS9023A can be configured for various audio sample delays with respect to the video signal. The audio sample delay is selected in "BUFSEL[1:0]" of Host Interface Register #6h. Table 13 lists the various audio sample delays.
2.3.2 Non-Standard Sample Distributions
Reset timing is detailed in Figure 20. Setting the RESET pin to LOW for a period of tRESET seconds forces the audio outputs LOW and re-initializes the internal control circuitry including returning all Host Interface Register values to their original default values. The RESET pin can be used for synchronizing multiple devices.
GS9023A
2.3.5 Interconnection with GS9032 or GS7005
Gennum Corporation has made every effort to maximize compatibility of the GS9023A with other Embedded Audio data streams. Unfortunately, due to variations in implementations (i.e. non-standard sample distributions) Gennum cannot guarantee compatibility with all Embedded Audio data streams.
2.3.3 Host Interface
The user should pay special attention when laying out the GS9023A to operate with the GS9032 or GS7005. The MSB to LSB convention is consistent between the GS9023A and GS9022 but reversed with respect to the GS9032 or GS7005. Layout complexity can be minimized by placing the GS9023A and the GS9032 or GS7005 on opposite sides of the printed circuit board (PCB).
2.3.6 Audio Clock and Video Clock Stability in Multiplex Mode
The Host Interface Registers allow for device configuration and provide status information. The GS9023A contains sixteen internal registers that are accessible through the Host Interface. Based on the mode of operation the registers have different functionality. In Multiplex Mode the registers are defined in Table 14 and in Demultiplex Mode the registers are defined in Table 15. The asynchronous Host Interface consists of a 4 bit address bus (ADDR[3:0]), 8 bit data bus (DATA[7:0]), read enable (RE), write enable (WE) and chip select (CS). The Host Interface access is independent of the PCLK or ACLK inputs. Read and write cycle timing is detailed in Figure 19. In a read cycle, CS is driven LOW tAS seconds after a valid address. RE is then driven LOW after tACS seconds for a minimum of tRD seconds. After tGQV seconds, the address register contents are output on the data bus. After a minimum of tRDH seconds, CS is driven HIGH to end the cycle. Similarly, in a write cycle, CS is driven LOW tAS seconds after a valid address. WE is then driven low after tACS seconds for a minimum of tWD seconds. Valid data must be present for a minimum of tDS seconds before WE is driven HIGH again. After a minimum of tWDH seconds, CS is driven HIGH to end the cycle.
Once the GS9023A is locked and processing audio, it is recommended that the audio clock frequency (ACLK at 128fs) remains stable and locked to video clock (VCLK). If VCLK is periodically switched or momentarily unstable, the audio clock phase locked loop circuit external to the GS9023A may be disrupted, causing ACLK to be at some arbitrary frequency. Under these conditions, operation of the GS9023A cannot be guaranteed and may result in corrupted audio. This is due to possible overflow/underflow condition occurring in the GS9023A internal FIFO, which is caused by the unstable audio clock input. If an overflow/ underflow condition occurs, the "BUFSTAT" bit in Host Interface Register #2h will be set HIGH. The internal FIFO can be reset automatically by setting the "BUFCTRL" bit in Host Interface Register #2h HIGH.
2.3.7 Interconnection with GS9020
The TRS_INSERT function of the GS9020 should be disabled when operating with the GS9023A. This is controlled through the Host Interface of the GS9020 and through the CLIP_TRS pin. If enabled this may cause the GS9020 to continue outputting valid TRS codes even when the input signal is removed.The GS9023A may not detect this loss of video input and could remain locked. When a valid video signal is re-applied to the GS9020, the GS9023A's internal audio buffers may not have been reset and will therefore be in an overflow or underflow condition.
TABLE 13 AUDIO VIDEO DELAY "BUFSEL[1:0]" 0 1 2 MODE (70 Sample) (26 Sample - Default) (20 Sample) MULTIPLEX (US) 875 250 187 DEMULTIPLEX (US) 541 312 250 MULTIPLEX/DEMULTIPLEX CONNECTION (US) 1416 563 437
1. NOTE: When the video signal is in D2 format, the delay is fixed at 70 samples (1416 us).
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3.
3.1
HOST INTERFACE TABLES
MULTIPLEX MODE
TABLE 14 MULTIPLEX MODE HOST INTERFACE REGISTERS ADDRESS 0h BIT 2-0 NAME VMOD[2:0] FUNCTION Video standard selection. See Table 1. Valid when "VSEL" is HIGH. Used in conjunction with "D2_TRS". "VMOD[2]" is the MSB and "VMOD[0]" is the LSB. Lock indicator. Same functionality as the LOCK pin. When set HIGH, the video standard has been identified, the start of a new video frame has been detected and the device is ready to multiplex audio. NOTE: LOCK will not be set HIGH unless at least one of the "CHACT(4-1)" bits (Address #1h) is HIGH. 4 EDHDEL EDH data delete. When set LOW, existing EDH packets are removed from the video stream. When set HIGH, existing EDH packets are passed through unless overwritten via the EDH_INS pin or the "EDHON" bit. Valid only when "CASCADE" (Address #4h bit 7) is LOW. Not used. TRS select. Same functionality as the TRS pin. Used to select video standard format.When set HIGH, TRS is added to a composite video signal. Valid only when "VSEL" is HIGH. Used in conjunction with "VMOD[2:0]". Video input format (external pin/internal register) configuration select. When set LOW, the video input format is configured via the VM[2:0] and TRS pins. When set HIGH, the video input format is configured via the "VMOD[2:0]" and "D2_TRS" bits. Audio channel enable. When set HIGH, the corresponding audio channel is multiplexed into the video signal. "CHACT(4)" is the MSB and "CHACT(1)" is the LSB. When set LOW, the GS9023A will not insert audio packets. NOTE: Do not rely on default value. Reprogram on power up or reset. 4 5 ACON EDHON Audio Control packet enable. When HIGH, the audio control packet is multiplexed in the video signal. EDH packet enable. Same functionality as the EDH_INS pin. When set HIGH, the GS9023A performs EDH functions according to SMPTE RP165. NOTE: Active picture and full field data words are updated from recalculated values but error flag information is replaced with the values programmed in Host Interface Registers #Eh and #Fh. 6 A4ON Extended audio packet enable. Same functionality as the AUXEN pin. When set HIGH, the extended audio packet is multiplexed in the video signal (24 bit audio). Arbitrary data packet enable. When set HIGH, an arbitrary data packet is multiplexed in the video signal. R/W 0 R/W R/W 0 0 R/W 0 R/W R/W DEFAULT 0
GS9023A
3
LOCK
R
0
5 6
RSV D2_TRS
- R/W
- 0
7
VSEL
R/W
0
1h
3-0
CHACT(4-1)
R/W
Fh
7
PKON
R/W
0
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TABLE 14 MULTIPLEX MODE HOST INTERFACE REGISTERS (CONTINUED) ADDRESS 2h BIT 0 1 2 NAME REVISION BUFSTAT VDET_MODE FUNCTION Device revision. When set HIGH, indicates the device is a GS9023A revision. Internal buffer status. When set HIGH, indicates that the internal audio sample buffer is in an overflow/underflow condition. Video detect mode. When set HIGH, the GS9023A will check the interval between the TRS on every line. If the interval is not consistent, the GS9023A assumes the input video has been switched and the internal audio sample buffer will be reset. Valid only when "RSEL" is set HIGH. 8-bit input selection. When set HIGH, the GS9023A will accept an 8-bit video input where DIN[9] is the MSB and DIN[2] is the LSB. DIN[1:0] should be set LOW. Valid only when "RSEL" is set HIGH. Not used. Mute on buffer error mode. When set LOW, the GS9023A will automatically set the embedded audio packets to zero (MUTE) when BUFSTAT is HIGH. When set HIGH, the user is required to set the MUTE function on detection of BUFSTAT set HIGH. Valid only when "RSEL" is set HIGH. It is recommended that this bit is kept HIGH whenever the video input to the device may undergo a synchronous switch (see Section 2.1.2.1). 6 BUFCTRL Internal buffer control mode. When set HIGH, the GS9023A will automatically reset the internal audio sample buffer when an overflow/underflow condition is detected. When set LOW, the internal audio sample buffer will not be reset unless the user asserts a device RESET. Valid only when "RSEL" is set HIGH. It is recommended that this bit is kept HIGH whenever the video input to the device may undergo a synchronous switch (see Section 2.1.2.1). 7 3h 3-0 7-4 RSEL AD20ID[3:0] AD4ID[3:0] Register select. When set HIGH, bits 2-6 of Host Interface register address #2h are valid. Designates the 4 LSBs of the audio data packet DID word. The 6 MSBs are internally generated. "AD20ID[3]" is the MSB and "AD20ID[0]" is the LSB. Designates the 4 LSBs of the extended audio data packet DID word. The 6 MSBs are internally generated. "AD4ID[3]" is the MSB and "AD4ID[0]" is the LSB. Designates the 4 LSBs of the audio control packet DID word. The 6 MSBs are internally generated. "ACID[3]" is the MSB and "ACID[0]" is the LSB. Not used. Audio mute enable. Same functionality as the MUTE pin. When set HIGH, the multiplexed audio and extended data packets are forced to zero. Audio control packet channel pair select. When set HIGH, audio control packet delay data for audio channels 3 and 4 is captured in registers Ah, Bh, Ch and Dh. When set LOW, audio control packet delay data for audio channels 1 and 2 is captured in registers #Ah, #Bh, #Ch and #Dh. Cascade select. When set HIGH, the GS9023A device is part of a cascaded architecture. New packets are multiplexed into the video signal starting at the first free location of the HANC space if there is sufficient remaining space to insert the packet. When set LOW, new packets are multiplexed into the video signal starting after EAV. Existing ancillary data packets are overwritten and the remaining ancillary space is cleared. Designates the 8 LSBs of the arbitrary data packet DID word. The 2 MSBs are internally generated. "PKTID[7]" is the MSB and "PKTID[0]" is the LSB. Video/audio delay mode. "BUFSEL[1]" is the MSB and "BUFSEL[0]" is the LSB. See Table 13. Not used. Audio data packet multiplexing error. The packet will not be multiplexed because of insufficient room in the HANC space. Error is cleared when read. Audio control packet multiplexing error. The packet will not be multiplexed because of insufficient room in the HANC space. Error is cleared when read. Not used. R/W R/W R/W 0 Fh Eh R/W 0 R/W R R R/W DEFAULT 1 0 0
GS9023A
3
8BIT_SEL
R/W
0
4 5
RSV MUTE_A/M
R/W 0
4h
3-0 4 5 6
ACID[3:0] RSV MUTE AC34/12
R/W R/W R/W
Fh
0 0
7
CASCADE
R/W
0
5h 6h
7-0 1-0 7-2
PKTID[7:0] BUFSEL[1:0] RSV ADERR ACERR RSV
R/W R/W R R -
0 1h
7h
0 1 7-2
0 0
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TABLE 14 MULTIPLEX MODE HOST INTERFACE REGISTERS (CONTINUED) ADDRESS 8h BIT 0 1 NAME RSV PKTPRTY Not used. Arbitrary data packet parity select. When set HIGH, a parity bit is generated for every user data word (UDW) of an arbitrary data packet. This overwrites any data input at the PKT[8] pin. Not used. Audio CH1/2 detection flag. When set HIGH, an audio signal has been detected. Audio CH3/4 detection flag. When set HIGH, an audio signal has been detected. Arbitrary data packet insertion line. Designates the horizontal line on which the GS9023A can multiplex arbitrary data packets in the video signal. Audio control packet delay. Designates the audio control packet delay data as specified in the SMPTE 272M standard. "DELA" corresponds to audio channels 1 and 2, while "DELB" corresponds to audio channels 3 and 4. "DELA/B[25]" is the MSB and "DELA/B[0]" is the LSB. Audio control packet synchronization data. Designates the sync mode bits (asx, asy), as defined in SMPTE 272M (Section 14.5), of channels 1/2 or 3/4 of the audio control packet. The bits are selected by "AC34/12" in register #4h. Audio control packet delay active. Designates the `e' bit of word "DELx0" of an audio control packet as defined in SMPTE 272 (Section 14.7). When set HIGH indicates valid audio delay data. Not used. EDH packet ancillary error flag. Error detected here. EDH packet ancillary error flag. Error detected already. EDH packet ancillary error flag. Internal error detected here. EDH packet ancillary error flag. Internal error detected already. EDH packet ancillary error flag. Unknown error status. Not used. EDH packet error flag. "CRCEDH_A" represents Full Field information. "CRCEDH_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet error flag. "CRCEDA_A" represents Full Field information. "CRCEDA_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet error flag. "CRCIDH_A" represents Full Field information. "CRCIDH_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet error flag. "CRCIDA_A" represents Full Field information. "CRCIDA_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet error flag. "CRCUES_A" represents Full Field information. "CRCUES_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet CRC valid flag. "CRCVLD_A" represents Full Field information. "CRCVLD_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). Not used. Full Field/Active Picture select. When set HIGH, the FF (Full Field) information is displayed in the above mentioned bits. When set LOW, the AP (Active Picture) information is displayed. FUNCTION R/W R/W 0 DEFAULT
5-2 6 7 9h Ah Bh Ch Dh 7-0 7-0 7-0 7-0 1-0 2
RSV AXST1/2 AXST3/4 PKTLINE[7:0] DELA/B[7:0] DELA/B[15:8] DELA/B[23:16] DELA/B[25:24] ACSYNCA/B
-
GS9023A
R R R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
3
ACDLY
R/W
0
7-4 Eh 0 1 2 3 4 7-5 Fh 0 1 2 3 4 5 6 7
RSV ANCI_EDH ANCI_EDA ANCI_IDH ANCI_IDA ANCI_UES RSV CRCEDH_A/B CRCEDA_A/B CRCIDH_A/B CRCIDA_A/B CRCUES_A/B CRCVLD_A/B RSV FF/AP_A/B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0
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3.2
DEMULTIPLEX MODE
TABLE 15 DEMULTIPLEX MODE HOST INTERFACE REGISTERS ADDRESS 0h BIT 2-0 NAME VMOD[2:0] FUNCTION Video standard selection. See Table 1. Valid when "VSEL" is HIGH. Used in conjunction with "D2_TRS". "VMOD[2]" is the MSB and "VMOD[0]" is the LSB. Lock indicator. Same functionality as the LOCK pin. When set HIGH, the video standard has been identified, the `lock' process selected by "ACTSEL" has been validated and the device is ready to demultiplex audio. See "ACTSEL" description. Ancillary data delete. Same functionality as the ANCI pin. When set HIGH, each ancillary data packet with a DID corresponding to either the audio packet DID, the extended audio packet DID or the arbitrary packet DID is removed from the video signal. When the "ADEL" bit is LOW, all ancillary data packets remain in the video signal. Valid only when "VSEL" is HIGH. Not used. TRS select. Same functionality as the TRS pin. Used to select video standard format. When set HIGH, TRS is removed from a composite video signal. Valid only when "VSEL" is HIGH. Used in conjunction with "VMOD[2:0]". Video input format (external pin/internal register) configuration select. When set LOW, the video input format is configured via the VM[2:0] and TRS pins. When set HIGH, the video input format is configured via the "VMOD[2:0]" and "D2_TRS" bits. Active audio channel flags. When set HIGH, the corresponding audio packets have been detected on the active video line. When set LOW, no corresponding audio packets have been detected on the active video line. The flags are updated on every frame. NOTE: When multiple audio groups are embedded in a video signal, the GS9023A will only indicate the presence of the first audio group. All audio groups will be properly demultiplexed, but the indicators for multiple groups will not be set correctly. 4 5 6 ACON EDHON A4ON Audio Control packet flag. When set HIGH, the audio control packet has been detected in the video signal. EDH flag. When set HIGH, EDH data has been detected in the video signal. Extended audio packet flag. When set HIGH, the extended audio packet has been detected on the active video line (24 bit audio). When set LOW, no extended audio packet has been detected on the active video line (24 bit audio). Not used. Device revision. When set HIGH, indicates the device is a GS9023A revision. Not used. Video detect mode. When set HIGH, the GS9023A will check the interval between the TRS on every line. If the interval is not consistent, the GS9023A assumes the input video has been switched and the internal audio sample buffer will be reset. Valid only when "RSEL" is set HIGH. Not used. Not used. Not used. Not used. Register select. When set HIGH, bit 2 of Host Interface register address #2h is valid. R R R 0 0 0 R/W R/W DEFAULT 0
3
LOCK
R
0
GS9023A
4
ADEL
R/W
0
5 6
RSV D2_TRS
- R/W
- 0
7
VSEL
R/W
0
1h
3-0
CHACT(4-1)
R
0
7 2h 0 1 2
RSV REVISION RSV VDET_MODE
R R/W 0 1
3 4 5 6 7
RSV RSV RSV RSV RSEL
R/W 0
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TABLE 15 DEMULTIPLEX MODE HOST INTERFACE REGISTERS (CONTINUED) ADDRESS 3h BIT 3-0 NAME AD20ID[3:0] FUNCTION Designates the 4 LSBs of the audio data packet DID word. The 6 MSBs are internally generated. "AD20ID[3]" is the MSB and "AD20ID[0]" is the LSB. Designates the 4 LSBs of the extended audio data packet DID word. The 6 MSBs are internally generated. "AD4ID[3]" is the MSB and "AD4ID[0]" is the LSB. Designates the 4 LSBs of the audio control packet DID word. The 6 MSBs are internally generated. "ACID[3]" is the MSB and "ACID[0]" is the LSB. Not used. Audio mute enable. Same functionality as the MUTE pin. When set HIGH, the demultiplexed audio and extended packet data are forced to zero. Audio lock process select. When set HIGH, the GS9023A `locks' by detecting the presence of an audio control packet corresponding to the DID configured in "ACID[3:0]" and occurring at the expected line and position as listed in Table 6. When set LOW, the GS9023A `locks' by counting the number of audio samples in a frame or multiple frames and validating the number of samples detected based on the video standard. Not used. Designates the 8 LSBs of the arbitrary data packet DID word. The 2 MSBs are internally generated. "PKTID[7]" is the MSB and "PKTID[0]" is the LSB. Video/audio delay mode. "BUFSEL[1]" is the MSB and "BUFSEL[0]" is the LSB. See Table 13. AES/EBU CRC select. When set HIGH, the C bit (channel status information) of each audio sample contains CRC information as defined in the AES3-1992 standard. Not used. Not used. Sample error. Incorrect number of audio samples detected. 8008 audio samples (48kHz) in 5 video frames for a 525 line video format. 1920 audio samples (48kHz) in 1 video frame for a 625 line video format. Audio channel 1/2 CRC error. Audio channel 3/4 CRC error. Audio packet DBN error. A DBN discontinuity was detected. Audio packet DC error. The number of UDW indicated does not match the number of words found in the data packet. Not used. Audio packet inversion bit error. An incorrect bit 9 inversion of bit 8 was detected in the audio packet. Not used. R/W R/W DEFAULT Fh
7-4
AD4ID[3:0]
R/W
Eh
GS9023A
4h
3-0
ACID[3:0]
R/W
Fh
4 5
RSV MUTE
R/W 0
6
ACTSEL
R/W
0
7 5h 7-0
RSV PKTID[7:0]
R/W 0
6h
1-0 2
BUFSEL[1:0] CRCADD
R/W R/W
1h 0
7-3 7h 4-0 5
RSV RSV SAMPERR
R 0
6 7 8h 0 1 2 3 7-4
ACRCERR1/2 ACRCERR3/4 A20DBNERR A20DCERR RSV A20B9ERR RSV
R R R R R -
0 0 0 0
0
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TABLE 15 DEMULTIPLEX MODE HOST INTERFACE REGISTERS (CONTINUED) ADDRESS 9h BIT 0 NAME ACCDBNERR FUNCTION Audio control packet DBN error. A DBN discontinuity was detected. NOTE: When a DBN discontinuity is detected, the VFLA/B pins remain valid (LOW). 1 3-2 4 6-5 7 Ah Bh Ch Dh 7-0 7-0 7-0 1-0 2 ACCDCERR RSV ACCB9ERR RSV A4B9ERR DELA/B[7:0] DELA/B[15:8] DELA/B[23:16] DELA/B[25:24] ACSYNCA/B Audio control packet DC error. The number of UDW indicated does not match the number of words found in the audio control packet. Not used. Audio control packet inversion bit error. An incorrect bit 9 inversion of bit 8 was detected in the audio control packet. Not used. Extended audio packet inversion bit error. An incorrect bit 9 inversion of bit 8 was detected in the extended audio packet. Audio control packet delay. Designates the audio control packet delay data as specified in the SMPTE 272M standard. DELA corresponds to audio channels 1 and 2, while DELB is the corresponds to audio channels 3 and 4. "DELA/B[25]" is the MSB and "DELA/B[0]" is the LSB. Audio control packet synchronization data. Designates the sync mode bits (asx, asy) as defined in SMPTE 272M (section 14.5) of channels 1/ 2 or 3/4 of the audio control packet. The bits are selected by "AC34/ 12". Audio control packet delay active. Designates the `e' bit of word "DELx0" of an audio control packet as defined in SMPTE 272 (section 14.7). When HIGH indicates valid audio delay data. Active channel 1/2 flag. Demultiplexed from the audio control packet, when present. Active channel 3/4 flag. Demultiplexed from the audio control packet, when present. Not used. Audio control packet and channel status channel pair select. When set LOW, the audio control packet delay data for audio channels 1 and 2 is captured in registers #Ah, #Bh, #Ch and #Dh. Registers #Eh and #Fh will display the channel status information for channels 1 and 2 respectively. When set HIGH, the audio control packet delay data for audio channels 3 and 4 is captured in registers #Ah, #Bh, #Ch and #Dh. Registers #Eh and #Fh will display the channel status information for channels 3 and 4 respectively. R R R R R R R R 0 0 0 0 0 0 0 0 R/W R DEFAULT 0
GS9023A
3
ACDLY
R
0
4 5 6 7
ACT1/2 ACT3/4 RSV AC34/12
R R R/W
0 0
0
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TABLE 15 DEMULTIPLEX MODE HOST INTERFACE REGISTERS (CONTINUED) ADDRESS Eh BIT 0 NAME CONPRO1/3 FUNCTION If AC34/12 bit of #Dh is set LOW AES/EBU channel 1 Consumer/Professional status. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 3 Consumer/Professional status. See AES-3 1992 standard. 1 AUDMOD1/3 If AC34/12 bit of #Dh is set LOW AES/EBU channel 1 normal/non-audio status. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 3 normal/non-audio status. See AES-3 1992 standard. 4-2 EMPH1/3[2:0] If AC34/12 bit of #Dh is set LOW AES/EBU channel 1 emphasis status. "EMPH1/3[2]" is the MSB and "EMP1/3[0]" is the LSB. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 3 emphasis status. "EMPH1/3[2]" is the MSB and "EMP1/3[0]" is the LSB. See AES-3 1992 standard. 5 SYNC1/3 If AC34/12 bit of #Dh is set LOW AES/EBU channel 1 sync status. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 3 sync status. See AES-3 1992 standard. 7-6 FSEL1/3[1:0] If AC34/12 bit of #Dh is set LOW AES/EBU channel 1 frequency select status. "FSEL1/3[1]" is the MSB and "FSEL1/3[0]" is the LSB. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 3 frequency select status. "FSEL1/3[1]" is the MSB and "FSEL1/3[0]" is the LSB. See AES-3 1992 standard. R 0 R 0 R 0 R 0 R/W R DEFAULT 0
GS9023A
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TABLE 15 DEMULTIPLEX MODE HOST INTERFACE REGISTERS (CONTINUED) ADDRESS Fh BIT 0 NAME CONPRO2/4 FUNCTION If AC34/12 bit of #Dh is set LOW AES/EBU channel 2 Consumer/Professional status. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 4 Consumer/Professional status. See AES-3 1992 standard. 1 AUDMOD2/4 If AC34/12 bit of #Dh is set LOW AES/EBU channel 2 normal/non-audio status. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 4 normal/non-audio status. See AES-3 1992 standard. 4-2 EMPH2/4[2:0] If AC34/12 bit of #Dh is set LOW AES/EBU channel 2 emphasis status. "EMPH2/4[2]" is the MSB and "EMP2/4[0]" is the LSB. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 4 emphasis status. "EMPH2/4[2]" is the MSB and "EMP2/4[0]" is the LSB. See AES-3 1992 standard. 5 SYNC2/4 If AC34/12 bit of #Dh is set LOW AES/EBU channel 2 sync status. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 4 sync status. See AES-3 1992 standard. 7-6 FSEL2/4[1:0] If AC34/12 bit of #Dh is set LOW AES/EBU channel 2 frequency select status. "FSEL2/4[1]" is the MSB and "FSEL2/4[0]" is the LSB. If AC34/12 bit of #Dh is set HIGH AES/EBU channel 4 frequency select status. "FSEL2/4[1]" is the MSB and "FSEL2/4[0]" is the LSB. See AES-3 1992 standard. R 0 R 0 R 0 R 0 R/W R DEFAULT 0
GS9023A
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ABSOLUTE MAXIMUM RATINGS
PARAMETER I/O Supply Voltage Internal Supply Voltage Input Voltage (any input) Operating Temperature Storage Temperature Lead Temperature (Soldering, 10 sec.) VALUE -0.3 to 7.0V -0.3 to 4.0V
GS9023A
-0.3 to VDDIO + 0.5V 0C to 70C -65C to 150C 230C
DC ELECTRICAL CHARACTERISTICS
TA = 0C to 70C unless otherwise shown.
PARAMETER I/O Supply Voltage I/O Supply Current
SYMBOL VDDIO IDDIO
CONDITIONS 5V Operating range VDDIO = 5V; PCLK = 54.0 MHz
MIN 4.75
TYP 5.00 25
MAX 5.25
UNITS V mA
I/O Supply Current
IDDIO
VDDIO = 5V; PCLK = 27.0 MHz
18
mA
I/O Supply Voltage Internal Supply Voltage Internal Supply Current Internal Supply Current Input Current Hi-Z Output Leakage Current Output Voltage, Logic High Output Voltage, Logic Low Input Voltage, Logic High Input Voltage, Logic Low Input Capacitance Output Capacitance I/O Capacitance
VDDIO VDDINT IDDINT IDDINT IN OZ VOH VOL VIH VIL CI CO CIO
3.3V Operating range
3.00 3.00
3.30 3.30 67 37
3.60 3.60
V V mA mA A A V V V V pF pF pF
PCLK = 54.0 MHz PCLK = 27.0 MHz -1 -1 OH = -3mA OL = 3mA VDDIO = Max (5.25V or 3.6V) VDDIO = Min. (4.75V or 3.0V) = 1MHz, VDDIO = 0V = 1MHz, VDDIO = 0V = 1MHz, VDDIO = 0V VDDIO - 0.4 2.0 -
-
1 1 0.4 0.8 10 10 10
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AC ELECTRICAL CHARACTERISTICS
VDDIO = 5V 5%, TA = 0C to 70C unless otherwise shown.
PARAMETER Video Clock Frequency Video Clock Pulse Width Low Video Clock Pulse Width High Video Input Data Setup Time Video Input Data Hold Time Video Output Data Delay Time Video Output Data Hold Time Audio Clock Frequency Audio Input Data Setup Time Audio Input Data Hold Time Audio Output Data Hold Time Audio Output Data Delay Time Address set up time Chip select set up time Read data access time Read data enable time Read data hold time Read pulse width Read cycle time Write data set up time Write data hold time Write pulse width Write cycle time Reset Pulse Width Device Latency
SYMBOL
CONDITIONS
MIN -
TYP 13 10
MAX 54 13 6.144 13 10 13 10
UNITS MHz ns ns
tPWL tPWH tS tH tOD tOH with 10 pF loading with 10 pF loading
7.4 7.4 3 1 3 -
GS9023A
ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us PCLKs
ts tH tOH tOD tAS tACS tGQV tGQLZ tRDH tRD tRC tDS tWDH tWD tWC tRESET Multiplexer Mode Demultiplexer Mode with 10pF loading with 10pF loading
3 1 3 3 3 1 1 20 30 3 1 20 30 1 13 10
NOTE: The following signals have the same AC electrical characteristics as the audio inputs and outputs: WCINA, WCINB, SAFA, SAFB, VFLA, VFLB, UDA, UDB, CSA, CSB, WCOUTA, WCOUTB.
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tH
DIN[9:0]
tS
PCLK
GS9023A
Figure 17 Video Data Input Setup & Hold Times
DOUT[9:0]
DATA VALID
tOH
PCLK
tOD
Figure 18 Video Data Output Delay & Hold Times
Read Cycle
Write Cycle
tRC
ADDR[3:0]
tWC tAS
tAS
CS
tACS
RE
tRD tACS tWD tDS tWDH
WE
tGQV tGQLZ
tRDH
Valid Data
DATA[7:0]
Valid Data
Figure 19 Host Interface Timing Diagram
VDDINT(min) VDDIO(min) VDDINT VDDIO
t RESET
t RESET
RESET
Figure 20 Reset Timing Diagram
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4.
PACKAGING INFORMATION
16.00 0.4 14.00 0.1 100 1 12 NOM View on A-A
GS9023A
16.00 0.4 14.00 0.1 A A 12 NOM
+0.05 0.125 -0.025 0 MIN 10 MAX 0.50 0.2 1.0 REF
1.40 0.1
1.70 MAX
0.5
0.18 +0.1 -0.05
0.1
100 pin LQFP (FY) Dimensions in millimetres
5.
REVISION HISTORY
VERSION 5 ECR 131679 DATE September 2003 CHANGES AND/OR MODIFICATIONS Added Section 2.1.2.1. Added Section 5. Discussed possible timing discrepancy when using multiple GS9023As to multiplex several audio channels. Expanded description of 'CHACT(4-1)' bits in demultiplex mode. Modified host interface register #Dh, #Eh, and #Fh descriptions (demultiplex mode only). 6 133575 May 2004 Removed VXST bit from register Oh of the host interface.Modified Section 2.1.5 and Section 2.2.7.
DOCUMENT IDENTIFICATION
DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright September 2003 Gennum Corporation. All rights reserved. Printed in Canada.
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